What we are offering

1. ESD consultancy to the I/O pad and internal layout design.
2. Standard protection device and IP transfer for human body model (HBM, machine model (MM) and Charged Device Model (CDM).
3. I/O cell library design and other customised I/O cells such as high speed, low parasitic and RF pads.
4. Failure analysis and root cause pin point on the packaged chips.
5. Design guideline for both ESD and latchups for the CMOS processes of 0.35um, 0.25um, 0.18um and 0.15um, included embedded and dual gate processes.